System on chip provides a powerful solution for many specialised digital devices. Incorporating all of the components of an entire computer system onto one chip enables the creation of digital devices with very focused utility most prominently in embedded devices. Portability is becoming an ever greater necessity for embedded devices. As such, power consumption is a key factor to be taken into to consideration during the design phase.

The kinds of embedded devices system on chip are found in are growing more numerous and more diverse by the day. The average consumer may be carrying three or more embedded devices on their person at any one time and in the course of a day they may use many more. One of the results of this is an ever greater increase in analogue interface with system on chip.

Not so long ago analogue appeared in fewer than 20 percent of high-end digital devices. By 2007 that figure was over 80 percent. It seems on the surface somewhat regressive but the ubiquity of devices employing system on chip means they are needed to interface with many of the phenomenon of our daily lives. Analogue is in a sense a bridge between the digital and the human world. The more we use digital the more we need analogue. Analogue to digital converters, digital to analogue converters, and other analogue IP's all need to be integrated with system on chip digital processing.

System on chip designs can obviously never keep up with the changing pace of embedded device functionality and nor would it be pragmatic for them to do so. Analogue devices, being what they are cannot change to adapt to new and different uses. The burden of flexibility then falls to the IP interface.

Of course this is no easy task either. To develop a custom IP interface from scratch typically costs millions which is why IP reuse is standard practice and why developing a flexible system on chip interface can be a profitable enterprise provided the large up front investment can be covered. Still, there is a trade off between flexibility of the IP interface and its robustness. The more flexible the interface the more prone it is to bugginess.

It is in the nature of analogue that analogue connections have to be laid out in very particular ways to prevent the various forms of interference that analogue suffers from but digital does not. Ensuring a device is properly functional at first operation becomes more challenging as the level of analogue connections to the system on chip device increases. The complexity of analogue IP adds to this challenge. Difficulties integrating system on chip with analogue IP is a regular cause of full chip design respins.

It seems that system on chip products will be required to interface with more and more analogue signals as we proceed into the future. This is likely to require ever greater flexibility from IP interfaces as well as more intricate design platforms to prevent the occurrence of bugs and inevitable chip design respins.